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| INTEGRATED CIRCUITS DATA SHEET TZA3012AHW 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver Preliminary specification 2002 Sep 10 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver FEATURES * Single 3.3 V power supply * I2C-bus and pin programmable fibre optic receiver. Dual limiter features * Dual limiting input with 12 mV sensitivity * Received Signal Strength Indicator (RSSI) * Loss Of Signal (LOS) indicator with threshold adjust * Differential overvoltage protection. Data and clock recovery features * Supports SHD/SONET rates at 155.52, 622.08, 2488.32 and 2666.06 Mbits/s (STM16/OC48 + FEC) * Supports Gigabit Ethernet at 1250 and 3125 Mbits/s * Supports Fibre Channel at 1062.5 and 2125 Mbits/s * ITU-T compliant jitter tolerance * Frequency lock indicator * Stable clock signal at the absence of input data * Recovered data and clock loop mode outputs. Demultiplexer features * 1 : 16, 1 : 10, 1 : 8 or 1 : 4 demultiplexing ratio * LVPECL or CML demultiplexer outputs * Frame detection for SDH/SONET and GE frames * Parity bit generation * Loop mode inputs on demultiplexer. TZA3012AHW Additional features with the I2C-bus * A-rateTM(1): supports any bit rate from 30 Mbits/s to 3.2 Gbits/s with one single reference frequency * Programmable with frequency resolution of 10 Hz * 4 reference frequency ranges * Adjustable swing of data, clock and parallel outputs * Programmable polarity of all RF I/Os * Swap of all RF I/O's for optimal connectivity * Swap of parallel bus for optimal connectivity * Slice level adjustment to improve Bit Error Rate (BER) * Mute function for a forced logic 0 output state * Programmable parity * Programmable 32 bits frame detection. APPLICATIONS * Any optical transmission system with bit rates between 30 Mbits/s and 3.2 Gbits/s * Physical interface IC in receive channels * Transponder applications * Dense Wavelength Division Multiplexing (DWDM) systems. (1) A-rate is a trademark of Philips Semiconductors GENERAL DESCRIPTION The TZA3012AHW is a fully integrated optical network receiver, containing a dual limiter, Data and Clock Recovery (DCR) and a demultiplexer with the ratios 1 : 16, 1 : 10, 1 : 8 or 1 : 4. The A-rate feature allows the IC to operate at any bit rate between 30 Mbits/s and 3.2 Gbits/s with one single reference frequency. The receiver supports loop modes with serial clock and data inputs and outputs. All clock signals are generated using a fractional N synthesizer with 10 Hz resolution giving a true, continuous rate operation. For full configuration flexibility, the receiver can be programmed via the I2C-bus. ORDERING INFORMATION TYPE NUMBER TZA3012AHW PACKAGE NAME HTQFP100 DESCRIPTION plastic, heatsink thin quad flat package; 100 leads; body 14 x 14 x 1.0 mm VERSION SOT638-1 2002 Sep 10 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... full pagewidth 2002 Sep 10 LOSTH1 7 RSSI INSEL IN1 IN1Q 12 9 10 LIM 16 IN2 17 IN2Q LIM RSSI BLOCK DIAGRAM Philips Semiconductors 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver CLOOP RSSI1 6 LOS1 5 DLOOP 87 DMRX0 ENBA DMRX1 ENLINQ DLOOPQ CLOOPQ 88 84 85 91 52 30 31 38 39 44, 46, 48, 53 55, 57, 59, 61, 64, 66, 68, 70 72, 77, 79, 81 PARITY PARITYQ LOS TZA3012AHW c d DMX 1 : 4 16 1:8 1 : 10 1 : 16 PARITY GENERATOR AND BUS SWAP 16 D00 to D15 SWITCH PHASE 2 DETECTOR 2 2 2 d c 16 45, 47, 49, 54 56, 58, 60, 62, 65, 67, 69, 71 73, 78, 80, 82 D00Q to D15Q POCLK POCLKQ FP FPQ COUT COUTQ DOUT DOUTQ INT LPF LOS LOSTH2 SCL(DR2) SDA(DR1) CS(DR0) UI i.c. 2 19 24 23 22 4 28, 29 14 8, 11, 15, 18 4 VCCA LIM = Limiting amplifier. RSSI = Receiving Signal Strength Indicator. LOS = Loss Of Signal detector. LPF = Low-Pass Filter. DMX = Demultiplexer. 20 RSSI2 21 LOS2 WINSIZE 13 33 34 27 2 CREFQ CREF 3 I2C-BUS FREQUENCY WINDOW DETECTOR 41 42 36 37 94 95 97 98 INTERRUPT CONTROLLER 1, 35, 40, 43, 51 75, 76, 83, 86, 89, 93, 96, 99 32 13 VDD VCCD ENLOUTQ VCCO VEE 92 3 RREF 90 25 26, 50, 63, 74, 100 MGU314 PRSCLOQ PRSCLO Preliminary specification TZA3012AHW INWINDOW Fig.1 Simplified block diagram of TZA3012AHW. Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver PINNING SYMBOL VEE VCCD PRSCLO PRSCLOQ UI LOS1 RSSI1 LOSTH1 VCCA IN1 IN1Q VCCA INSEL WINSIZE RREF VCCA IN2 IN2Q VCCA LOSTH2 RSSI2 LOS2 CS(DR0) PIN DESCRIPTION SYMBOL SDA(DR1) SCL(DR2) VDD VEE INWINDOW i.c. i.c. DMXR0 DMXR1 VCCO CREF CREFQ VCCD FP FPQ PARITY PARITYQ VCCD POCLK POCLKQ VCCD D00 D00Q D01 D01Q D02 D02Q VEE die common ground plane pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 supply voltage (digital part) prescaler output prescaler output inverted user interface selection input LOS output of first input channel received signal strength indicator output of first input channel LOS threshold input for first input channel supply voltage (analog part) input of first channel input of first channel inverted supply voltage (analog part) input selector wide and narrow frequency detect window selection input reference resistor input supply voltage (analog part) input of second channel input of second channel inverted supply voltage (analog part) LOS threshold input for second input channel received signal strength indicator output of second input channel LOS output of second input channel chip select (data rate select 0) 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PIN 23 24 I2C-bus TZA3012AHW DESCRIPTION serial data (data rate select 1) I2C-bus serial clock (data rate select 2) supply voltage (digital) ground frequency window detector output internally connected internally connected DEMUX ratio select 0 DEMUX ratio select 1 supply voltage (clock generator) reference clock input reference clock input inverted supply voltage (digital part) frame pulse output frame pulse output inverted parity output parity output inverted supply voltage (digital part) parallel clock output parallel clock output inverted supply voltage (digital part) parallel data output 00 parallel data output 00 inverted parallel data output 01 parallel data output 01 inverted parallel data output 02 parallel data output 02 inverted ground 2002 Sep 10 4 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver SYMBOL VCCD ENBA D03 D03Q D04 D04Q D05 D05Q D06 D06Q D07 D07Q VEE D08 D08Q D09 D09Q D10 D10Q D11 D11Q D12 D12Q VEE VCCD VCCD PIN 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 DESCRIPTION supply voltage (digital part) byte alignment enable input parallel data output 03 parallel data output 03 inverted parallel data output 04 parallel data output 04 inverted parallel data output 05 parallel data output 05 inverted parallel data output 06 parallel data output 06 inverted parallel data output 07 parallel data output 07 inverted ground parallel data output 08 parallel data output 08 inverted parallel data output 09 parallel data output 09 inverted parallel data output 10 parallel data output 10 inverted parallel data output 11 parallel data output 11 inverted parallel data output 12 parallel data output 12 inverted ground supply voltage (digital part) supply voltage (digital part) INT VCCD COUT COUTQ VCCD DOUT DOUTQ VCCD VEE 92 93 94 95 96 97 98 99 ENLINQ 91 SYMBOL D13 D13Q D14 D14Q D15 D15Q VCCD CLOOP CLOOPQ VCCD DLOOP DLOOPQ VCCD ENLOUTQ PIN 77 78 79 80 81 82 83 84 85 86 87 88 89 90 TZA3012AHW DESCRIPTION parallel data output 13 parallel data output 13 inverted parallel data output 14 parallel data output 14 inverted parallel data output 15 parallel data output 15 inverted supply voltage (digital part) loop mode clock input loop mode clock input inverted supply voltage (digital part) loop mode data input loop mode data input inverted supply voltage (digital part) line loop back enable input (active LOW) diagnostic loop back enable input (active LOW) interrupt output supply voltage (digital part) recovered clock output recovered clock output inverted supply voltage (digital part) recovered data output recovered data output inverted supply voltage (digital part) 100 ground 2002 Sep 10 5 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver TZA3012AHW 90 ENLOUTQ 88 DLOOPQ 86 VCCD 85 CLOOPQ 91 ENLINQ 98 DOUTQ 95 COUTQ 87 DLOOP 100 VEE 99 VCCD 84 CLOOP 97 DOUT 94 COUT 96 VCCD 93 VCCD 92 INT 89 VCCD 83 VCCD handbook, full pagewidth VCCD PRSCLO PRSCLOQ UI LOS1 RSSI1 LOSTH1 VCCA IN1 1 2 3 4 5 6 7 8 9 76 VCCD 75 VCCD 74 VEE 73 D12Q 72 D12 71 D11Q 70 D11 69 D10Q 68 D10 67 D09Q 66 D09 65 D08Q 64 D08 63 VEE 62 D07Q 61 D07 60 D06Q 59 D06 58 D05Q 57 D05 56 D04Q 55 D04 54 D03Q 53 D03 52 ENBA 51 VCCD VEE 50 MGU315 82 D15Q 80 D14Q 78 D13Q D02 48 81 D15 79 D14 IN1Q 10 VCCA 11 INSEL 12 WINSIZE 13 RREF 14 VCCA 15 IN2 16 IN2Q 17 VCCA 18 LOSTH2 19 RSSI2 20 LOS2 21 CS(DR0) 22 SDA(DR1) 23 SCL(DR2) 24 VDD 25 VEE 26 INWINDOW 27 i.c. 28 i.c. 29 DMXR0 30 DMXR1 31 VCCO 32 CREF 33 CREFQ 34 VCCD 35 FP 36 FPQ 37 PARITY 38 PARITYQ 39 VCCD 40 POCLK 41 POCLKQ 42 VCCD 43 D00 44 D00Q 45 D01 46 D01Q 47 D02Q 49 TZA3012AHW Fig.2 Pin configuration. 2002 Sep 10 6 77 D13 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver FUNCTIONAL DESCRIPTION The TZA3012AHW receives data from an incoming bit stream with a bit rate from 30 Mbits/s up to 3.2 Gbits/s. The IC has two limiting amplifier inputs. A DCR section synchronizes the internal clock generator with the incoming data. The recovered serial data and clock are demultiplexed with a ratio of 1 : 16, 1 : 10, 1 : 8 or 1 : 4. Configuring the TZA3012AHW by I2C-bus or by pins The IC features two types of user interface, I2C-bus control or pin programming. Interface selection is set by pin UI (User Interface); see Table 1. The I2C-bus control is operational and A-rate functionality is enabled if pin UI is left open or connected to VCC. If pin UI is connected to VEE pins DR0, DR1 and DR2 are available for selection of eight pre-programmed bit rates. Table 1 UI LOW HIGH Truth table for pin UI MODE pre-programmed I2C-bus control PIN 22 DR0 CS PIN 23 DR1 SDA PIN 24 DR2 SCL Table 3 TZA3012AHW Truth table for pins DR2, DR1 and DR0 (UI = VEE) DR1 LOW LOW HIGH HIGH LOW LOW HIGH HIGH DR0 LOW HIGH LOW HIGH LOW HIGH LOW HIGH PROTOCOL STM1/OC3 STM4/OC12 STM16/OC48 STM16 + FEC GE 10GE Fibre Channel Fibre Channel BIT RATE (Mbits/s) 155.52 622.08 2488.32 2666.06 1250.00 3125.00 1062.50 2125.00 DR2 LOW LOW LOW LOW HIGH HIGH HIGH HIGH After power-up, the TZA3012AHW initiates a Power-On Reset (POR) sequence to restore the default settings of the I2C-bus registers, regardless of the user interface. For the defaults see Table 11. Limiting amplifiers The TZA3012AHW contains two limiting amplifiers. The dual limiter input provides rapid switching between two line connections, supporting protection switching, for example. The active RF input is selected with pin INSEL, see Table 4. Only one channel is on at a time, the unused channel automatically goes into sleep mode, to reduce power dissipation. Table 4 INSEL HIGH LOW Truth table for pin INSEL LIMITER channel 1 active channel 2 active SELECTED INPUT PINS IN1(Q) IN2(Q) In I2C-bus control mode, the chip is configured by using the I2C-bus pins SDA and SCL. Pin CS (chip select) has to be HIGH during I2C-bus read or write actions. When pin CS is set LOW, the programmed configuration remains active, but signals SDA and SCL are ignored. In this way, all ICs in the application with the same I2C-bus address (e.g. other TZA3012) are individually accessible. The I2C-bus address is given in Table 2. Table 2 A6 1 I2C-bus address of TZA3012AHW A5 0 A4 1 A3 0 A2 0 A1 0 A0 0 R/W X A detailed list of all I2C-bus registers and the meaning of their contents can be found in Chapter "I2C-bus registers". Some functions of the TZA3012AHW can be controlled by using a pin or the I2C-bus. In these cases, an extra I2C-bus bit called I2C Apart from pin INSEL, the input can also be selected through I2C-bus register LIMCNF (C2H), bits I2CINSEL and INSEL. Bit I2CINSEL sets pin or I2C-bus precedence and bit INSEL the actual channel selection. Again, only one channel is activated at a time. Both limiting amplifiers can be activated simultaneously by setting I2C-bus bit BOTHON of the same I2C-bus register. Although both amplifier channels are active now, only the channel selected by INSEL is used as input for the DCR section. This configuration allows very fast switching (so called `hot` switching) between the two channels. Without BOTHON switching needs 4 s. 2002 Sep 10 7 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver Table 5 Channel selection INSEL PIN 0 1 x x INSEL I2C x x 0 1 SELECTED CHANNEL channel 2 channel 1 channel 2 channel 1 TZA3012AHW Both logarithmic detectors are active simultaneously, as opposed to the limiting amplifiers, where only one channel is active at a time. This allows the selection of the input with the strongest signal. Loss Of Signal (LOS) indicator Besides the analog RSSI output, a digital LOS indication is present on the TZA3012AHW. The RSSI level is internally compared with a LOS threshold, which can be set by an external resistor (pins LOSTH1 and LOSTH2) or by means of an internal D/A converter. Bits I2CREFLVL1 and I2CREFLVL2 from I2C-bus registers BDH and BFH enable the 8-bit D/A converters, of which the value needs to be programmed into I2C-bus registers BCH (LOSTH1) or BEH (LOSTH2). Threshold levels can be set individually for each channel. If the received signal strength is below the threshold value, LOS will be HIGH. A default hysteresis of 2.5 dB is applied in the comparator. I2C-bus registers LIMLOS1CNF (BDH) and LIMLOS2CNF (BFH) provide more flexibility, i.e. a programmable hysteresis of 0 to 6 dB in steps of 0.85 dB. If needed, the polarity of the LOS outputs can be inverted by I2C-bus bits LOS1POL and LOS2POL from I2C-bus registers BDH and BFH. I2CINSEL I2C 0 0 1 1 To achieve optimum receiver sensitivity for any bit rate, the bandwidth of the amplifiers is automatically scaled with the bit rate. Wideband noise of the optical front-end (photo detector and transimpedance amplifier) is thus reduced for lower bit rates. When using the I2C-bus, the bandwidth of the amplifier can be set independently of the bit rate with I2C-bus bits AMPOCT in I2C-register LIMCNF (C2H). The highest bandwidth is selected per default at power-up. Received Signal Strength Indicator (RSSI) The signal strength at each of the two inputs is measured with a logarithmic detector and presented at pins RSSI1 and RSSI2 for channels 1 and 2, respectively. The RSSI reading has a sensitivity of typical 17 mV/dB for a Vi(p-p) range of 5 mV to 500 mV (see Fig.3). VRSSI can be calculated using the following formula: V i(p-p) V RSSI = V RSSI(30 mV) + S RSSI x 20log ---------------30 mV handbook, full pagewidth MBL555 1.2 VRSSI (V) 0.9 SRSSI 0.6 0.3 0 5 10 30 102 300 500 103 Vi(p-p) (mV) Fig.3 VRSSI as a function of Vi(p-p). 2002 Sep 10 8 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver Setting LOSTH reference level by external resistor If the built-in D/A converter is not used, the reference voltage level to pin LOSTH1 (or LOSTH2) can be set by connecting an external resistor (R2) from the relevant pin to ground. The voltage on the pin is determined by the resistor ratio between R2 and R1 (see Fig.4). For resistor R1 a value of 10 to 20 k is recommended, yielding a current of 120 to 60 A. R2 The LOSTH voltage equals ------- x V ref R1 Voltage Vref represents a temperature stabilized and accurate reference voltage of 1.2 V. The minimum threshold level corresponds to 0 V and the maximum to 1.2 V. Hence, the value of R2 may not be higher than R1. The accuracy of the LOSTH voltage depends mainly on the matching of the two external resistors. Slice level adjustment TZA3012AHW Due to asymmetrical noise in some optical transmission systems, a pre-detection signal-to-noise ratio improvement can be achieved by adding a DC offset to the input signal. This is done by the slice level circuit in the TZA3012AHW. The required offset depends on the photo detector characteristics in the optical front-end and the amplitude of the received signal. Hence, the slice level has been made adjustable between -50 mV and +50 mV in 512 steps of 0.2 mV. Bits SL1 and SL2 of I2C-bus registers BDH or BFH enable the slice function of the respective channel. The slice level itself is set by sign and magnitude convention. The sign, either positive or negative (polarity), is set in I2C-bus registers BDH or BFH, bits SL1SGN or SL2SGN. The magnitude, 0 to 50 mV in 256 steps, is set by an 8-bit D/A converter through I2C-bus register C0H or C1H, respectively. The introduced offset is not present on inputs IN and INQ, in order not to affect the logarithmic RSSI detector, which would detect the offset as a valid input signal. Data and Clock Recovery (DCR) The TZA3012AHW recovers the clock and data contents from the incoming bit stream, see Fig.5. The DCR uses a combined frequency and phase locking scheme, providing reliable and quick data acquisition on any bit rate between 30 Mbits/s and 3.2 Gbits/s. Initially, at power-up, coarse adjustment of the free running VCO frequency is required. This is achieved by the Frequency Window Detector (FWD) circuit. The FWD is a conventional frequency locked PLL. The FWD checks the VCO frequency, which has to be within a 1000 ppm (parts per million) window around the desired frequency. The FWD then compares the divided VCO frequency (also available on pins PRSCLO and PRSCLOQ) with the reference frequency on pins CREF and CREFQ, usually 19.44 MHz. If the VCO frequency is found to be outside this window, the FWD disables the Data Phase Detector (DPD) and forces the VCO to a frequency within the window. As soon as the `in window' condition occurs, which is visible on pin INWINDOW, the DPD starts acquiring lock on the incoming bit stream. Since the VCO frequency is very close to the expected bit rate, the phase acquisition will be almost instantaneous, resulting in quick phase lock to the incoming data stream. VCCA RSSI LOS 1.2 V Vref RREF I R1 10 k LOS compare LOSTH1 LOSTH2 R2 GND MGU318 Fig.4 Setting the LOSTH reference level by external resistors. Apart from using resistors (R1 and R2) to set the LOS threshold, an accurate external voltage source can also be used. If no resistor is connected to LOSTH1 (or LOSTH2), or an external voltage higher than 23 x VCC is applied to the pin, the LOS detection circuit (including the RSSI reading for that channel) is automatically switched off to reduce power dissipation. This `auto power off' only works if UI = VEE, i.e. manual control of the TZA3012AHW. In I2C-bus mode, several I2C-bus bits allow flexible configuration. 2002 Sep 10 9 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver Although the VCO is now locked to the incoming bit stream, the FWD is still supervising the VCO frequency and takes over control if the VCO drifts outside the predefined frequency window. This might occur during a `loss of signal' situation. Due to the FWD, the VCO frequency is always close to the required bit rate, enabling rapid phase acquisition if the lost input signal returns. TZA3012AHW Due to the loose coupling of 1000 ppm, the reference frequency does not need to be highly accurate or stable. Any crystal-based oscillator that generates a reasonably accurate frequency (e.g. 100 ppm) will do. handbook, full pagewidth LIMITING AMPLIFIER DATA IN DATA PHASE DETECTOR OCTAVE DIVIDER /M VOLTAGE CONTROLLED OSCILLATOR (VCO) MAIN Frac DIVIDER N REFERENCE DIVIDER CREF(Q) /R REFERENCE INPUT up FREQUENCY WINDOW down DETECTOR up down RECOVERED DATA RECOVERED CLOCK DOUT(Q) COUT(Q) to DEMULTIPLEXER CHARGE PUMP LOOP FILTER + CHARGE PUMP PRSCLO(Q) PRESCALER OUTPUT MGU346 Fig.5 Block diagram of data and clock recovery. Fractional N synthesizer The DCR section has a fractional N synthesizer as frequency acquisition aid for the A-rate functionality. This allows the DCR to synchronize on incoming data, regardless of its bit rate. Any combination of bit rate and reference frequency is possible, due to the 22 bits fractional N synthesizer, allowing approximately 10 Hz frequency resolution. The LSB (bit K0) should be set to logic 1 to avoid limit cycles (cycles of less than maximum length). This leaves 21 bits (K<21:1>) available for free programming. Programming the DCR Programming the DCR involves four dividers; the reference frequency divider R, the main divider N, fractional divider K and the octave divider M. The first step is to determine in which octave the desired bit rate fits, see Tables 6 and 7. The value for R is usually 1; see Section "Programming the reference clock" for detailed information. Once the octave and the reference frequency are known, the main division ratio N and the fractional part K can be calculated according to the flowchart given in Fig.7. 2002 Sep 10 10 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver Table 6 List of most common optical transmission protocols BIT RATE (Mbits/s) 3125.00 2970.00 2666.06 2488.32 2380.00 2125.00 1485.00 1380.00 1300.00 1250.00 1062.50 1062.50 1062.50 622.08 595.00 425.00 265.63 212.50 200.00 155.52 125.00 125.00 106.25 OCTAVE 0 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 3 3 4 4 4 4 4 5 Fig.6 28.125 56.25 112.5 225 450 handbook, 6 halfpage 5 TZA3012AHW Table 7 Octave definition M 1 2 4 8 16 32 64 LOWEST BIT RATE (Mbits/s) 1800 900 450 225 112.5 56.25 28.125 HIGHEST BIT RATE (Mbits/s) 3200 1800 900 450 225 112.5 56.25 OCTAVE PROTOCOL 10GE 2xHDTV STM16/OC48 +FEC STM16/OC48 DV-6000 Fibre Channel HDTV D-1 Video DV-6010 Gigabit Ethernet Fibre Channel OptiConnect ISC STM4/OC12 DV-6400 Fibre Channel OptiConnect Fibre Channel ESCON/SBCON STM1/OC3 FDDI Fast Ethernet Fibre Channel 1 2 3 4 5 6 4 3 2 1 0 900 1800 3200 Mbits/s MGU316 Commonly used line rates and allocation of octaves along a logarithmic bit rate scale. 2002 Sep 10 11 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver TZA3012AHW handbook, full pagewidth CALCULATE BIT RATE bit rate x M x R = n.k fref n is integer part k is fractional part yes k=0? no NILFRAC = 1 NILFRAC = 0 no k 0.25 ? yes no k 0.75 ? yes k = k + 0.5 k = k - 0.5 N=2xn+1 no 0.25 < k < 0.75 yes N=2xn N=2xn N=2xn-1 j = 21 k=kx2 no k1? yes Kj = 1 k=k-1 Kj = 0 decimal to binary conversion of fractional part j=j-1 no j=0? yes K0 = 1 Write Kj into registers B3H, B4H and B5H Convert N to binary and write into registers B1H and B2H END MGU551 Fig.7 Flowchart for calculating N and K. 2002 Sep 10 12 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver TZA3012AHW Example 1: An SDH or SONET link has a bit rate of 2488.32 Mbits/s (STM16/OC48) and consequently fits in octave number 0, so M = 1. Suppose the reference frequency provided at pins CREF(Q) is 77.76 MHz. This means that the reference division R needs to be 4. The values of n and k can be calculated from the flowchart: 2488.32 Mbits x 1 x 4 bit rate x M x R n.k = --------------------------------------- = -------------------------------------------------------- = 128 77.76 MHz f ref Since k = 0 in this example, no fractional functionality is required, bit NILFRAC should be logic 1 (register B3H). N = 2 x n and no correction is required. Consequently the appropriate values are: R = 4 (register B6H), M = 1 (register B0H) and N = 256 (registers B1H and B2H). Example 2: An SDH STM16 or SONET OC48 link with FEC has a bit rate of 2666.057143 Mbits/s (15/14 x 2488.32 Mbits/s) and consequently fits in octave number 0, so M = 1. Suppose the reference frequency provided at pins CREF(Q) is 38.88 MHz. This means that the reference division R, needs to be 2. The values of n and k can be calculated from the flowchart: bit rate x M x R 2666.05714283 Mbits x 1 x 2 n.k = --------------------------------------- = ---------------------------------------------------------------------------- = 137.1428571 f ref 38.88 MHz This means that n = 137, k = 0.1428571 and bit NILFRAC should be logic 0 (register B3H). Since k < 0.25, k is corrected to 0.6428571, while the corrected N becomes N = 273. Consequently the appropriate values are: R = 2 (register B6H), M = 1 (register B0H), N = 273 (registers B1H and B2H) and K = 10 1001 0010 0100 1001 0011 (registers B3H, B4H and B5H). The FEC bit rate is usually quoted to be 2666.06 Mbits/s. Due to round off errors, this leads to a slightly different value for k than in the example. Example 3: A Fibre Channel link has a bit rate of 1062.50 Mbits/s and consequently fits in octave number 1, so M = 2. Suppose the reference frequency provided at pins CREF(Q) is 19.44 MHz. This means that the reference division R needs to be 1. The values of n and k can be calculated from the flowchart: bit rate x M x R 1062.50 Mbits x 2 x 1 n.k = --------------------------------------- = -------------------------------------------------------- = 109.3106996 f ref 19.44 MHz This means that n = 109, k = 0.3107 and bit NILFRAC should be logic 0 (register B3H). Since k is between 0.25 and 0.75, k does not need to be corrected and N = 2 x n = 218. Consequently the appropriate values are: R = 1 (register B6H), M = 2 (register B0H) and N = 218 (registers B1H and B2H). K = 01 0011 1110 0010 1000 0001 (registers B3H, B4H and B5H). Example 4: A non standard transmission link has a bit rate of 3012 Mbits/s and consequently fits in octave number 0, so M = 1. Suppose the reference frequency provided at pins CREF(Q) is 20.50 MHz. This means that the reference division R needs to be 1. The values of n and k can be calculated from the flowchart: 3012 Mbits x 1 x 1 bit rate x M x R n.k = --------------------------------------- = ----------------------------------------------- = 146.9268293 20.50 MHz f ref This means that n = 146, k = 0.9268293 and bit NILFRAC should be logic 0 (register B3H). Since k is larger than 0.75, k needs to be corrected to 0.4268293 and N = 2 x n + 1 = 293. Consequently the appropriate values are: R = 1 (register B6H), M = 1 (register B0H) and N = 293 (registers B1H and B2H). K = 01 1011 0101 0001 0010 1011 (registers B3H, B4H and B5H). If the I2C-bus is not used, the DCR can be set up for the eight pre-programmed bit rates by pins DR0, DR1 and DR2 with an applied reference frequency of 19.44 MHz (see Table 3). 2002 Sep 10 13 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver Programming the reference clock Pre-programmed operation requires the use of any reference frequency between 18 and 21 MHz connected to pins CREF(Q). Pre-programmed operation in an SDH/SONET application requires the use of a 19.44 MHz reference clock, see Table 3. In I2C-bus control mode, 4 ranges of clock frequencies can be used by programming R through bits REFDIV in register B6H; see Table 8. Internally, the reference frequency is always divided to the lowest range, from 18 to 21 MHz. Table 8 REFDIV 00 01 10 11 Truth table for bits REFDIV DIVISION FACTOR R 1 2 4 8 SDH/SONET REFERENCE FREQUENCY 19.44 MHz 38.88 MHz 77.76 MHz 155.52 MHz REFERENCE FREQUENCY RANGE 18...21 MHz 36...42 MHz 72...84 MHz 144...168 MHz TZA3012AHW The VCO will be directly locked to the reference signal instead of the incoming bit stream. Apart from pin WINSIZE, this mode can be invoked by I2C-bus bits I2CWINSIZE and WINSIZE from I2C-bus register B6H. Table 9 Truth table for pin WINSIZE FREQUENCY WINDOW 0 ppm 1000 ppm WINSIZE LOW HIGH Accurate clock generation during loss of signal, bit AUTOWIN A zero window size is especially interesting in the absence of input data, since the frequency of the recovered clock will be equal to the reference frequency including its tolerance. The option AUTOWIN makes the window size dependent on the LOS status of the active limiter channel. If the optical input signal is lost, the FWD automatically selects the 0 ppm window size; i.e. direct lock on to the reference frequency. This results is a stable and defined output clock during `loss of signal' situations, while automatically reverting back to normal DCR operation when the input signal returns. The accuracy of the reference frequency needs to be better than 20 ppm if the application is to comply with ITU-T recommendations. INWINDOW signal The status of the FWD circuit is reflected in the state of pin INWINDOW; HIGH for an `in window' situation and LOW whenever the VCO is outside the defined frequency window. Jitter performance The TZA3012AHW has been optimized for best jitter tolerance performance. For all SDH/SONET bit rates, the jitter tolerance exceeds compliance with ITU-T standard G.958. Prescaler outputs The prescaler output PRSCLO(Q) is the VCO frequency divided by the main division factor. It can be used as an accurate reference for another PLL, since it corresponds to the recovered data rate. If needed, the polarity of the prescaler outputs can be inverted by bit PRSCLOINV from register CBH. If no prescaler information is desired, the output can be disabled by bit PRSCLOEN from the same register. Apart from these settings, the type of output, the termination mode and the signal amplitude can be set. These parameters follow the settings of the parallel demultiplexer outputs. For programming details, see Section "Configuring the parallel bus". Programming the FWD The default width of the window for frequency acquisition is 1000 ppm around the desired bit rate. This window size can be changed between 4000 and 250 ppm by I2C-bus bits WINDOWSIZE from I2C-bus register B6H. This allows for loose or tight coupling of the VCO to the applied reference clock. Another feature is to define a window width of 0 ppm, by means of pin WINSIZE (pin 13). This effectively removes the dead zone from the FWD, rendering the FWD into a classical PLL. 2002 Sep 10 14 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver Demultiplexer TZA3012AHW The demultiplexer converts the serial input bit stream to parallel format (1 : 16, 1 : 10, 1 : 8, 1 : 4). The output data is available on a scalable bus, of which the output driver type can be either LVPECL or CML. Apart from the deserializing function, the demultiplexer comprises a parity calculator and a frame header detection circuit. The calculated parity, EVEN, is output at pins PARITY and PARITYQ, whereas occurrence of the frame header pattern in the data stream results in a 1 clock cycle wide pulse on outputs FP and FPQ. If ENBA is HIGH, automatic byte (word) alignment takes place, formatting the parallel output to logical bytes or words. Apart from pin ENBA, this mode can be invoked by I2C-bus bits I2CENBA and ENBA from I2C-bus register A8H. To support most commonly used transmission systems and protocols, the demultiplexing ratio can be set and the frame header pattern programmed to any 32 or 10-bit pattern (see Section "Frame detection"). If required, the demultiplexer output can be forced into a fixed logic state by the mute function. Adjustable demultiplexing ratio The demultiplexing ratio of the TZA3012AHW can be configured by pins DMXR0 and DMXR1 or bits DMXR of I2C-bus register DMXCNF (I2C-bus register A8H), according to Table 10. Bit I2CDMXR of register A8H enables programming of the demultiplexing ratio by the bits DMXR. The parallel output bus is always centred around the middle (VEE, pin 63) for optimum layout connectivity. Table 10 lists the active outputs for the various demultiplexing ratios. In I2C-bus mode, the 1 : 16 ratio is default. The LSB appears on the output with the lowest pin number. The bus order can be changed with I2C-bus bit BUSSWAP in register DMXCNF (A8H). Bit BUSSWAP reverses the order of bits from MSB to LSB or vice versa, to allow for optimal layout connectivity. The highest supported parallel bus speed is 400 Mbits/s. Therefore, the 1 : 4 demultiplexing ratio is only supported for bit rates up to 1.6 Gbits/s. Table 10 Setting the demultiplexing ratio DMXR1 (PIN) LOW LOW HIGH HIGH DMXR0 (PIN) LOW HIGH LOW HIGH DMXR (REG A8H) 00 01 10 11 DEMULTIPLEXING RATIO 1:4 1:8 1 : 10 1 : 16 ACTIVE OUTPUTS D06...D09 D04...D11 D03...D12 D00...D15 (all) ACTIVE OUTPUT PINS LSB...MSB 59...67 55...71 53...73 44...82 Frame detection Byte alignment is enabled if the Enable Byte Alignment (ENBA) input is HIGH. Whenever a 32-bit or 10-bit sequence matches the programmed header pattern, the incoming data is formatted into logical bytes or words and a frame pulse is generated on differential outputs FP and FPQ. Any header pattern can be programmed through I2C-bus registers HEADER0 to HEADER3. It is possible to enter a "don't care" for any bit position, e.g. to program a header pattern that is much shorter than 32 or 10 bits or to program a pattern with a gap in it. For this, it is necessary to program I2C-bus registers HEADERX0 to HEADERX3, as in the example shown in Fig.8. The contents of the don't care I2C-bus registers serve as a masking pattern on top of the programmed framing pattern. The default frame header pattern is F6F62828H, corresponding to the middle section of the standard SDH/SONET frame header (the last two A1 bytes plus the first two A2 bytes). 2002 Sep 10 15 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver TZA3012AHW handbook, full pagewidth HEADER MSB (Bit 32) HEADER3 0 0 0 1 0 1 1 1 0 HEADER LSB (Bit 1) 1 1 0 0 0 1 0 HEADER0 HEADERX3 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 HEADERX0 X 0 0 1 0 X 1 1 0 1 1 0 0 0 X X received data data stream MGU548 Fig.8 Example of programming the framing pattern: the symbol `X' represents a "don't care". If ENBA is LOW, no active alignment takes place. However, if the framing pattern happens to occur in the formatted data, a frame pulse will still be output on pins FP and FPQ. For 10-bit oriented protocols, such as Gigabit Ethernet, the frame header detection works on a 10-bit pattern sequence. These 10 bits should be programmed into I2C-bus registers HEADER3 and HEADER2 (two LSBs only), the remaining 22 bits are ignored. Again, a `don't care' pattern overlay can be programmed in I2C-bus registers HEADERX3 and HEADERX2 (two bits). Since some 10-bit oriented protocols use a DC balancing code, the detection pattern could appear in complementary form in the data stream. By setting bit CMPL in I2C-bus register DMXCNF (A8H), the header detection will scan the data stream for the programmed pattern as well as its complement simultaneously. Therefore, either occurrence will result in a `byte' alignment and a corresponding frame pulse on pins FP and FPQ. The default pattern (after power-up) is `0011111010b' or K28.5 character plus alternating 010. This is the only pattern containing five consecutive bits of the same sign. Receiver framing in SDH/SONET applications Figure 9 shows a typical SDH/SONET reframe sequence involving byte alignment. Frame and byte boundary detection is enabled on the rising edge of ENBA and remains enabled while ENBA is HIGH. Boundaries are recognized on receipt of the second A2 byte and FP goes HIGH for one POCLK cycle. In 1 : 16 mode, the first two A2 bytes in the frame header are the first data word to be reported with the correct alignment on the outgoing data bus (D00 to D15). In 1 : 8 mode the first A2 byte is the first aligned data byte (D04 to D11), while in 1 : 4 mode the most significant nibble of the first A2 byte is the first aligned data (D06 to D09). When interfacing with a section terminating device, ENBA must remain HIGH for a full frame after the initial frame pulse. This is to allow the section terminating device to verify internally that frame and byte alignment are correct (see Fig.10). Byte boundary detection is disabled on the first FP pulse after ENBA has gone LOW. Figure 11 shows frame and byte boundary detection activated on the rising edge of ENBA, and deactivated by the first FP pulse after ENBA has gone LOW. 2002 Sep 10 16 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver TZA3012AHW handbook, full pagewidth serial clock ENBA 32 bits serial data A1 invalid data A1 A1 A2 A2 valid data 1 : 16 D00 to D15 (1:16) A2 28 28 A2 POCLK (1:16) FP (1:16) 1:4 D06 to D09 (1:4) 2 A2 8 2 A2 8 POCLK (1:4) FP (1:4) MGU550 Fig.9 Frame and byte detection in SDH/SONET application. handbook, halfpage boundary detection enabled handbook, halfpage boundary detection enabled ENBA FP MGU340 ENBA FP MGU341 Fig.10 ENBA timing with section terminating device. Fig.11 Alternate ENBA timing. 2002 Sep 10 17 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver Parity generation Outputs PARITY(Q) provide the EVEN parity of the byte/word that is currently available on the parallel bus. With bit PARINV of I2C-bus register C9H, the parity can be made ODD. If no parity is required, I2C-bus bit PAREN can disable this output, to reduce power dissipation. Configuring the parallel bus Several options exist that allow flexible configuration of the parallel bus and associated outputs. The options for POCLK(Q), D00(Q) to D15(Q), FP(Q), PARITY(Q) and PRSCLO(Q) are: output driver type, termination mode, output amplitude, signal polarity, bits order, mute and selective enabling or disabling. These options are set in registers DMXCNF (A8H), IOCNF (C9H) and IOCNF3 (C8H). Bit MFOUTMODE selects the CML or LVPECL output driver (default LVPECL). Bit MFOUTTERM sets the termination mode, standard LVPECL or floating termination, or in case of CML, DC or AC coupled. The four MFS bits adjust the amplitude in all cases. I2C-bus bit PDEN disables the output driver. This is not the same as the MUTE option, which forces a logic 0 state. The default output amplitude is 800 mV (p-p) single-ended. Bit PDINV inverts the polarity of the parallel data, POCLKINV inverts the clock, effectively shifting the clock edge by half a clock cycle, and changing the rising edge to a falling edge. This might resolve a parallel bus timing problem. The bus clock can even be disabled by I2C-bus bit POCLKEN. The same features, with other I2C-bus bits, hold for FP and FPQ and the parity outputs PARITY and PARITYQ. Loop mode I/Os TZA3012AHW The "diagnostic loop back" is activated by setting pin ENLINQ to LOW. In this case, the demultiplexer will select inputs DLOOP(Q) and CLOOP(Q) instead of taking the input from the DCR. The "line loop back" mode is activated by setting ENLOUTQ to LOW. In this case the recovered clock and serial data will be available at output pins DOUT(Q) and COUT(Q). Configuring the RF I/Os The polarity of the individual serial data and clock I/Os can be inverted via the I2C-bus. The position of the data and clock outputs (or inputs) can be swapped. This solves connectivity problems with other ICs. Registers IOCNF0 (CBH) and IOCNF1 (CAH) program all RF I/O configurations. When the RF input data and clock are swapped by means of bit CDINSWAP (register CAH), the signals present at pins CLOOP(Q) are assumed to be data and the signals at pins DLOOP(Q) are assumed to be clock. The same holds for swapping the RF outputs. Data is output at pins COUT(Q) and clock at pins DOUT(Q). The RF CML outputs have an adjustable signal amplitude from 60 mV (p-p) to 1000 mV (p-p) (single-ended) in 16 steps, by bits RFS and RFSWING (register CBH). The default amplitude is 80 mV (p-p) single-ended. The termination scheme is AC coupled. 2002 Sep 10 18 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver CMOS control inputs Most CMOS control inputs have an internal pull-up resistor. An open circuit equals a HIGH input. Only the LOW state needs to be actively forced. This holds for pins UI, INSEL, WINSIZE, DMXR0, DMXR1, ENBA, ENLOUTQ, ENLINQ and CS. The same is true for pins DR0, DR1 and DR2 in pre-programmed mode (UI = LOW). In I2C-bus mode (UI = HIGH), pins SCL and SDA comply with the I2C-bus interface standard. Power supply connections Four separate supply domains (VDD, VCCD, VCCO, and VCCA) provide isolation between the various functional blocks. Each supply domain should be connected to a common VCC via separate filters. All supply pins, including the exposed die pad, must be connected. The die pad should be connected with the lowest inductance possible. Since the die pad is also used as the main ground return of the chip, the connection should have a low DC impedance as well. The voltage supply levels should be in accordance with the values specified in Chapters "Characteristics" and "Limiting values". All external components should be surface mounted devices, preferably of size 0603 or smaller. The components must be mounted as closely to the IC as possible. Interrupt controler The configurable interrupt controler is based on five status flags: * Loss of signal on channel 1 * Loss of signal on channel 2 * DCR in window indication * Switching of limiters indication * Temperature alarm. This controler contains three I2C-bus registers, namely interrupt register (address 00H), status register (address 01H), and mask register (address CCH). In the I2C-bus status register the history is stored, the reason for an interrupt. The status register shows the present status of the receiver. The mask register determines the masking of the flags generating an interrupt on pin INT. See Tables 12, 13 and 29. TZA3012AHW The MSB of I2C-bus register INTMASK determines the output type of pin INT: standard CMOS output or open-drain output. The latter is the default value, which provides for multiple receivers sharing a common interrupt signal wire, with a 3.3 k pull-up resistor (INT is active LOW in this case). The polarity of the INT output can be inverted by bit INTPOL from register CCH. The interrupt and status register can be polled by an I2C-bus read action. After the read action the interrupt register is reset by clearing all interrupt flags. If the 'alarm` is still present, the flag is immediately set again in the I2C-bus interrupt register. The I2C-bus status register is not reset since it always shows the present status of the receiver. I2C-bus registers Setting pin UI HIGH or leaving the pin open allows I2C-bus programming. The I2C-bus registers can be accessed via the 2-wire I2C-bus interface, pins SCL and SDA, if CS (chip select) is HIGH during read or write actions. Table 11 shows the I2C-bus register list. 2002 Sep 10 19 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver Table 11 I2C-bus register list ADDRESS 00H 01H A0H NAME INTERRUPT STATUS HEADER3 FUNCTION interrupt register (see Table 12) status register (see Table 13) programmable header, MSB 1 : 10 ratio A1H HEADER2 programmable header 1 : 10 ratio A2H A3H A4H HEADER1 HEADER0 HEADERX3 programmable header programmable header, LSB programmable header don't care, MSB 1 : 10 ratio A5H HEADERX2 programmable header don't care 1 : 10 ratio A6H A7H A8H B0H B1H B2H B3H B4H B5H B6H BCH BDH BEH BFH C0H C1H C2H C8H C9H CAH CBH CCH HEADERX1 HEADERX0 DMXCNF DIVCNF MAINDIV1 MAINDIV0 FRACN2 FRACN1 FRACN0 DCRCNF LIMLOS1TH LIMLOS1CNF LIMLOS2TH LIMLOS2CNF LIMSLICE1 LIMSLICE2 LIMCNF IOCNF3 IOCNF2 IOCNF1 IOCNF0 INTMASK programmable header don't care programmable header don't care, LSB demultiplexer configuration register (see Table 14) main divider division ratio N (MSB) (see Table 16) main divider division ratio N (see Table 17) fractional divider division ratio K (see Table 18) fractional divider division ratio K (see Table 19) fractional divider division ratio K (see Table 20) DCR configuration register (see Table 21) limiter 1 loss of signal threshold register limiter 1 loss of signal configuration register (see Table 22) limiter 2 loss of signal threshold register limiter 2 loss of signal configuration register (see Table 23) limiter 1 slice level register limiter 2 slice level register limiter configuration register (see Table 24) I/O configuration register 3; parallel outputs (see Table 25) I/O configuration register 2; parallel outputs (see Table 26) I/O configuration register 1; RF serial I/Os (see Table 27) I/O configuration register 0; RF serial I/Os (see Table 28) interrupt masking register (see Table 29) TZA3012AHW DEFAULT RANGE n.a. n.a. 1111 0110 0011 1110 1111 0110 10xx xxxx 0010 1000 0010 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1011 0000 0001 0000 0000 1000 0000 0000 0000 0000 0000 0000 1100 0000 0000 0000 1101 0000 0000 0000 1101 0000 0000 0000 0000 0000 1000 0000 1100 1010 1010 0000 0000 0010 0011 0101 0000 n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. [128 to 511] n.a. n.a. n.a. n.a. [0 to 255] n.a. [0 to 255] n.a. [0 to 255] [0 to 255] n.a. n.a. n.a. n.a. n.a. n.a. octave and loop mode configuration register (see Table 15) 0000 0000 2002 Sep 10 20 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver Table 12 Register INTERRUPT (address: 00H) BIT 7 6 5 4 3 2 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 PARAMETER DESCRIPTION Loss Of Signal (LOS) on channel 1 no signal present (loss of signal condition) signal present Loss Of Signal (LOS) on channel 2 no signal present (loss of signal condition) signal present DCR frequency indication frequency outside predefined window (unlocked) frequency inside predefined window (locked) switching of limiters indication indication of switching from one limiter to the other no switching temperature alarm junction temperature 130 C junction temperature <130 C TZA3012AHW NAME LOS1 LOS2 INWINDOW LIMSEL TALARM reserved 2002 Sep 10 21 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver Table 13 Register STATUS (address: 01H) BIT 7 6 5 4 3 2 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 PARAMETER DESCRIPTION Loss Of Signal (LOS) on channel 1 no signal present (loss of signal condition) signal present Loss Of Signal (LOS) on channel 2 no signal present (loss of signal condition) signal present DCR frequency indication frequency inside predefined window (locked) frequency outside predefined window (unlocked) limiter autoselect indication limiter 1 active limiter 2 active temperature alarm junction temperature 130 C junction temperature <130 C TZA3012AHW NAME LOS1 LOS2 INWINDOW LIMSEL TALARM reserved 2002 Sep 10 22 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver Table 14 Register DMXCNF (address: A8H, default value: 0BH; see also last row of table) BIT 7 6 5 4 3 2 1 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 1 0 demultiplexing ratio 1 0 1 0 1 : 16 1 : 10 1:8 1:4 demultiplexing ratio programming through I2C-bus interface through external pins DMXR0 and DMXR1 header detection in 1 : 10 Gigabit Ethernet mode simultaneously check for complementary header check programmed header only parallel bus swapping D00 = MSB, D15 = LSB (swapped) D15 = MSB, D00 = LSB (normal) demultiplexer mute parallel outputs mute; parallel outputs forced to logic 0 no mute enable byte alignment byte alignment enabled byte alignment disabled ENBA control through I2C-bus interface through external pin ENBA PARAMETER DESCRIPTION TZA3012AHW NAME DMXR I2CDMXR CMPL BUSSWAP DMXMUTE ENBA I2CENBA default value 2002 Sep 10 23 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver Table 15 Register DIVCNF (address: B0H, default value: 00H; see also last row of table) BIT 7 6 5 4 3 2 0 0 0 0 1 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 enable loop mode inputs loop mode inputs enabled loop mode inputs disabled enable loop mode outputs loop mode outputs enabled loop mode outputs disabled loop mode control through I2C-bus interface through external pins ENLINQ and/or ENLOUTQ 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 PARAMETER DESCRIPTION division ratio octave divider M; octave selection M = 1, octave no. 0 M = 2, octave no. 1 M = 4, octave no. 2 M = 8, octave no. 3 M = 16, octave no. 4 M = 32, octave no. 5 M = 64, octave no. 6 TZA3012AHW NAME DIV_M reserved ENLOOPIN ENLOOPOUT I2CLOOPMODE default value Table 16 Register MAINDIV1 (address: B1H, default value: 01H; see also last row of table) BIT 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 1 PARAMETER DESCRIPTION NAME DIV_N default value N8 division ratio divider, N; N8 = MSB Table 17 Register MAINDIV0 (address: B2H, default value: 00H; see also last row of table) BIT 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 PARAMETER DESCRIPTION NAME DIV_N default value N7 N6 N5 N4 N3 N2 N1 N0 division ratio divider, N; N0 = LSB 2002 Sep 10 24 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver Table 18 Register FRACN2 (address: B3H, default value: 80H; see also last row of table) BIT 7 NF 1 0 1 0 0 0 0 0 0 0 6 x 5 4 3 2 1 0 PARAMETER DESCRIPTION NILFRAC control bit (NF) no fractional N functionality fractional N functionality TZA3012AHW NAME DIV_K NILFRAC K21 K20 K19 K18 K17 K16 fractional divider, K; K21 = MSB default value Table 19 Register FRACN1 (address: B4H, default value: 00H; see also last row of table) BIT 7 K15 0 6 K14 0 5 0 4 0 3 0 2 0 1 K9 0 0 K8 0 PARAMETER DESCRIPTION fractional divider, K NAME DIV_K default value K13 K12 K11 K10 Table 20 Register FRACN0 (address: B5H, default value: 00H; see also last row of table) BIT 7 K7 0 6 K6 0 5 K5 0 4 K4 0 3 K3 0 2 K2 0 1 K1 0 0 K0 0 PARAMETER DESCRIPTION fractional divider, K; K0 = LSB NAME DIV_K default value 2002 Sep 10 25 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver Table 21 Register DCRCNF (address: B6H, default value: 0CH; see also last row of table) BIT 7 6 5 4 3 2 0 0 1 1 1 1 1 1 1 0 0 1 0 0 1 0 1 0 4000 ppm 2000 ppm 1000 ppm 500 ppm 250 ppm manual frequency window size selection PARAMETER DESCRIPTION frequency window size, relative to bit rate TZA3012AHW NAME WINDOWSIZE WINSIZE window size according to `WINDOWSIZE' (default value 1000 ppm); PLL frequency loosely coupled to reference crystal window size = 0 ppm; PLL frequency directly synthesized from reference crystal WINSIZE control bit I2CWINSIZE through I2C-bus interface through external pin WINSIZE automatic frequency window size selection AUTOWIN enabled disabled reference frequency divider REFDIV R = 8; reference frequency = 155.52 MHz R = 4; reference frequency = 77.76 MHz R = 2; reference frequency = 38.88 MHz R = 1; reference frequency = 19.44 MHz 0 1 0 1 0 1 1 0 0 0 1 0 1 0 0 0 0 1 1 0 0 default value 2002 Sep 10 26 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver TZA3012AHW Table 22 Register LIMLOS1CNF (address: BDH, default value: 0DH; see also last row of table) BIT 7 6 5 4 3 2 1 0 1 0 1 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 0 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 PARAMETER DESCRIPTION loss of signal detection on channel 1 LOS detection enabled LOS detection disabled loss of signal threshold level control bit channel 1 through I2C-bus interface by internal DAC; register BCH HYS1 through analog voltage on pin LOSTH1 loss of signal detection hysteresis channel 1 0 dB 0.85 dB 1.7 dB 2.5 dB 3.4 dB 4.2 dB 5.1 dB 6 dB slice level of channel 1 slice level enabled slice level disabled slice level sign of channel 1 positive slice level negative slice level polarity of LOS channel 1 inverted polarity normal polarity default value LOS1POL SL1SGN SL1 I2CREFLVL1 NAME LOS1 2002 Sep 10 27 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver TZA3012AHW Table 23 Register LIMLOS2CNF (address: BFH, default value: 0DH; see also last row of table) BIT 7 6 5 4 3 2 1 0 1 0 1 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 0 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 PARAMETER DESCRIPTION loss of signal detection on channel 2 LOS detection enabled LOS detection disabled loss of signal threshold level control bit channel 2 through I2C-bus interface by internal DAC; register BEH HYS2 through analog voltage on pin LOSTH2 loss of signal detection hysteresis channel 2 0 dB 0.85 dB 1.7 dB 2.5 dB 3.4 dB 4.2 dB 5.1 dB 6 dB slice level of channel 2 slice level enabled slice level disabled slice level sign of channel 2 positive slice level negative slice level polarity of LOS channel 2 inverted polarity normal polarity default value LOS2POL SL2SGN SL2 I2CREFLVL2 NAME LOS2 2002 Sep 10 28 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver Table 24 Register LIMCNF (address: C2H, default value: 08H; see also last row of table) BIT 7 6 5 4 3 2 0 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 x 0 0 1 0 1 x PARAMETER DESCRIPTION amplifier octave selection octave no. 0; 1800 to 3200 Mbits/s octave no. 1; 900 to 1800 Mbits/s octave no. 2; 450 to 900 Mbits/s octave no. 3; 225 to 450 Mbits/s octave no. 4; 30 to 225 Mbits/s limiter channel selection channel 1 active channel 2 active limiter channel selection control bit through I2C-bus interface; bit INSEL through external pin INSEL single/dual limiter selection both channels active single channel active, according to INSEL TZA3012AHW NAME AMPOCT INSEL I2CINSEL BOTHON reserved default value Table 25 Register IOCNF3 (address: C8H, default value: 0CH; see also last row of table) BIT 7 6 5 4 3 0 0 1 1 0 1 0 1 0 0 0 0 0 1 1 0 0 0 parallel output termination LVPECL mode: floating, CML mode: AC coupled LVPECL mode: standard, CML mode: DC coupled parallel output mode CML; Current Mode Logic LVPECL; Positive Emitter Coupled Logic default value MFOUTMODE 2 0 0 1 1 1 0 0 0 1 0 0 1 0 1 0 mV (p-p) minimum signal level; 120 mV (p-p) default signal level; 800 mV (p-p) maximum signal level; 1000 mV (p-p) reserved MFOUTTERM PARAMETER DESCRIPTION parallel output signal amplitude MFS NAME 2002 Sep 10 29 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver Table 26 Register IOCNF2 (address: C9H, default value: AAH; see also last row of table) BIT 7 6 5 4 3 2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 inverted normal parallel data output enable enabled disabled parallel clock output polarity inverted normal parallel clock output enable enabled disabled parity output polarity inverted normal parity output enable enabled disabled frame pulse output polarity inverted normal frame pulse output enable enabled disabled PARAMETER DESCRIPTION parallel data output polarity TZA3012AHW NAME PDINV PDEN POCLKINV POCLKEN PARINV PAREN FPINV FPEN default value 2002 Sep 10 30 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver Table 27 Register IOCNF1 (address: CAH, default value: 00H; see also last row of table) BIT 7 6 5 4 3 2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 inverted normal loop mode data input polarity inverted normal loop mode input clock and data swap swapped clock and data input pairs normal clock and data input loop mode clock output polarity inverted normal loop mode data output polarity inverted normal loop mode output clock and data swap swapped clock and data output pairs normal clock and data output PARAMETER DESCRIPTION loop mode clock input polarity TZA3012AHW NAME CININV DININV CDINSWAP COUTINV DOUTINV CDOUTSWAP reserved default value 2002 Sep 10 31 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver Table 28 Register IOCNF0 (address: CBH, default value: 23H; see also last row of table) BIT 7 6 5 4 3 0 0 1 1 0 1 0 1 0 0 0 0 1 0 0 0 1 1 2 0 0 1 1 0 1 1 0 0 1 1 PARAMETER DESCRIPTION RF serial output signal amplitude: minimum signal level; 60 mV (p-p) default signal level; 250 mV (p-p) maximum signal level; 1000 mV (p-p) prescaler output polarity inverted normal prescaler output enable enabled disabled RF serial output swing high swing low swing TZA3012AHW NAME RFS PRSCLOINV PRSCLOEN RFSWING reserved default value 2002 Sep 10 32 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver Table 29 Register INTMASK (address: CCH, default value: A0H; see also last row of table) BIT 7 6 5 4 3 2 1 0 mask LOS1 signal 1 0 1 0 1 0 1 0 1 0 0 INT polarity mode 1 0 1 0 0 Note 1. Signal is not processed by the interrupt controller. 1 0 1 0 0 0 0 inverted normal INT output mode standard CMOS output open-drain output not masked masked; note 1 mask LOS2 signal not masked masked; note 1 mask INWINDOW signal not masked masked; note 1 mask LIMSEL signal not masked masked; note 1 mask Temperature Alarm not masked masked; note 1 PARAMETER DESCRIPTION TZA3012AHW NAME MLOS1 MLOS2 MINWINDOW MLIMSEL MTALARM reserved INTPOL INTOUT default value 2002 Sep 10 33 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver TZA3012AHW without using the I2C-bus Although the TZA3012AHW is intended to be programmed via an I2C-bus, a lot of features can be accessed from external pins. This chapter lists the functions of the TZA3012AHW if the User Interface (UI) pin is LOW. FEATURES WITHOUT THE I2C-BUS (UI = VEE): * 1 of 4 pre-programmed SDH/SONET bit rates; STM1/OC3, STM4/OC12, STM16/OC48, STM16/OC48 +FEC (DR2...DR0) * 1 of 4 pre-programmed bit rates; Fibre Channel, double Fibre Channel, Gigabit Ethernet, 10-Gigabit Ethernet (DR2...DR0) * 1 of 4 demultiplexing ratios; 1 : 16, 1 : 10, 1 : 8 or 1 : 4 (DMXR1 and DMXR0) * Input channel selection (INSEL) * Received signal strength indicator, independently for channels 1 and 2 * Loss of signal detection threshold for each input channel individually (LOSTH1 and LOSTH2) TZA3012AHW * Automatic disable of unused logarithmic detector (LOSTH1 and LOSTH2) * Loop mode serial input and output configuration (ENLINQ and ENLOUTQ) * Automatic byte alignment for SDH/SONET or Gigabit Ethernet (ENBA) * Frame detection for SDH/SONET (pattern is A1A1A2A2) or Gigabit Ethernet * EVEN parity generation * LVPECL parallel outputs with 800 mV (p-p) single-ended signal (DC coupled termination to VCC - 2 V) * CML serial RF outputs with typical 80 mV (p-p) single-ended signal (AC coupled load) * In window detection (INWINDOW) * Sizeable frequency window, 1000 ppm or 0 ppm (WINSIZE) * Temperature alarm (pin INT; open-drain) * Supported reference frequency from 18 to 21 MHz. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VCCA, VCCD, VCCO, VDD Vn supply voltages DC voltage on pins D00 to D15, D00Q to D15Q, POCLK, POCLKQ, FP, FPQ, PARITY, PARITYQ, PRSCLO and PRSCLOQ pins LOSTH1, LOSTH2 and RREF pins RSSI1 and RSSI2 pins UI, INSEL, WINSIZE, CS, SDA, SCL, DMXR0, DMXR1, ENBA, ENLOUTQ and ENLINQ pins LOS1, LOS2 and INWINDOW pin INT In input current on pins IN1, IN1Q, IN2 and IN2Q pins CREF, CREFQ, CLOOP, CLOOPQ, DLOOP and DLOOPQ pin INT Tamb Tj Tstg ambient temperature junction temperature storage temperature -30 -20 -2 -40 -40 -65 +30 +20 +2 +85 +125 +150 mA mA mA C C C VCC - 2.5 VCC + 0.5 -0.5 -0.5 -0.5 -0.5 -0.5 VCC + 0.5 VCC + 0.5 VCC + 0.5 VCC + 0.5 VCC + 0.5 V V V V V V PARAMETER MIN. -0.5 MAX. +3.6 V UNIT 2002 Sep 10 34 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver THERMAL CHARACTERISTICS SYMBOL Rth(j-a) Notes 1. In compliance with JEDEC standards JESD51-5 and JESD51-7. PARAMETER thermal resistance from junction to ambient CONDITIONS notes 1 and 2 TZA3012AHW VALUE 16 UNIT K/W 2. Four-layer Printed Circuit Board (PCB) in still air with 36 plated vias connected with the heatsink and the second and fourth layer in the PCB. CHARACTERISTICS VCC = 3.14 to 3.47 V; Tamb = -40 to +85 C; Rth(j-a) 16 K/W; all characteristics are specified for the default settings (note 1); all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. SYMBOL Supplies ICCA ICCD ICCO IDD ICC(tot) Ptot VIL VIH IIL IIH VOL VOH VOL IOH Vo(p-p) supply current (analog) supply current (digital) supply current (oscillator) supply current (digital) total supply current total power dissipation see Figs 12 and 14 - - - - - - - 0.7VCC VIL = 0 V VIH = VCC IOL = 1 mA IOH = -1 mA IOL = 1 mA VOH = VCC single-ended with 50 external load; ENLOUTQ = LOW; see Figs 15 and 19; note 2 single-ended to VCC 20% to 80% 80% to 20% - - 0 20 350 25 5 400 1.3 - - - - - - - - - - - 0.3VCC - -200 10 mA mA mA mA mA W PARAMETER CONDITIONS MIN. TYP. MAX. UNIT CMOS input; pins UI, DR0, DR1, DR2, INSEL, WINSIZE, CS, DMXR0, DMXR1, ENBA, ENLOUTQ and ENLINQ LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current V V A A V V CMOS output; pins LOS1, LOS2, INWINDOW and INT LOW-level output voltage HIGH-level output voltage 0.2 VCC 0.2 10 - VCC - 0.2 - 0 - - - - 80 Open-drain output; pin INT LOW-level output voltage HIGH-level output current V A mV Serial output; pins COUT, COUTQ, DOUT and DOUTQ default output voltage swing (peak-to-peak value) Zo tr tf output impedance rise time fall time 80 - - 100 130 130 120 - - ps ps 2002 Sep 10 35 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver SYMBOL tD-C PARAMETER data-to-clock delay CONDITIONS (COUT(Q) and DOUT(Q)) between differential cross-overs (see Fig.21) - MIN. TYP. 170 TZA3012AHW MAX. - UNIT ps duty cycle COUT and COUTQ between differential cross-overs 40 50 60 % Serial input; pins CLOOP, CLOOPQ, DLOOP, DLOOPQ Vi(p-p) VI ZI td tsu th input voltage (peak-to-peak value) input voltage input impedance delay time set-up time hold time duty cycle CLOOP and CLOOPQ single-ended to VCC see Fig.22 see Fig.22 see Fig.22 between differential cross-overs single-ended with 50 external load to VCC; AC coupled (see Fig.19) or DC coupled (see Fig.20); note 3 single-ended to VCC 20% to 80% 80% to 20% single-ended 50 VCC - 2 40 280 - - 40 - - 50 340 30 30 50 1000 VCC + 0.25 60 400 - - 60 mV V ps ps ps % CML mode parallel output; pins D00(Q) to D15(Q), FP(Q), PARITY(Q), POCLK(Q) and PRSCLO(Q) Vo(p-p) default output voltage swing (peak-to-peak value) - 800 - mV Zo tr tf fP VOH VOL Vo(p-p) output impedance rise time fall time parallel bit rate 80 - - - 100 250 250 - 120 - - 400 VCC - 0.9 VCC - 1.7 - ps ps Mbits/s LVPECL mode parallel output; pins D00(Q) to D15(Q), FP(Q), PARITY(Q), POCLK(Q) and PRSCLO(Q) HIGH-level output voltage LOW-level output voltage default output voltage swing (peak-to-peak value) 50 termination to VCC - 2V (see Fig.16) 50 termination to VCC - 2V (see Fig.16) VCC - 1.2 - VCC - 2.2 - 800 V V mV LVPECL floating (see - Fig.13); single-ended with 50 external load to VCC; AC coupled (see Fig.18) or DC coupled (see Fig.17); note 3 20% to 80% 80% to 20% - - - tr tf fP rise time fall time parallel bit rate 350 350 - - - 400 ps ps Mbits/s 2002 Sep 10 36 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver SYMBOL PARAMETER CONDITIONS MIN. TYP. TZA3012AHW MAX. UNIT Timing parallel output; pins D00(Q) to D15(Q), FP(Q), PARITY(Q), POCLK(Q) and PRSCLO(Q) (see Fig.23) tD-C tD-C skew data-to-clock delay D00 to D15/POCLK data-to-clock delay D06 to D09/POCLK duty cycle POCLK channel to channel skew D00 and Dn (between channels) channel to channel skew D06 and D09 (between channels) DMX 1 : 16, 1 : 10, 1 : 8; note 4 DMX 1 : 4; note 4 DMX 1 : 16, 1 : 10, 1 : 8; see Fig.23; note 4 DMX 1 : 4; see Fig.23; note 4 100 150 40 - 100 180 50 - 250 300 60 200 ps ps % ps skew - - 50 ps Reference; pin RREF Vref reference voltage 10 to 20 k resistor to VEE 1.17 1.22 1.28 V I2C-bus pins SCL and SDA VIL VIH Vhys VOL IL Ci LOW-level input voltage HIGH-level input voltage hysteresis of Schmitt trigger inputs SDA LOW-level output voltage (open-drain) leakage current input capacitance IOL = 3 mA 0 0.7VCC 0.05VCC 0 -10 - - 1.3 0.6 0.6 0.6 0 100 0.6 20 20 1.3 - 0 0.1VCC 0.2VCC 37 - - - - - - - - - - - - - - - - - - - - - 0.3VCC VCC - 0.4 +10 10 V V V V A pF I2C-bus timing fSCL tLOW tHD;STA tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tr tf tBUF Cb tSP VnL VnH 2002 Sep 10 SCL clock frequency SCL LOW time hold time START condition SCL HIGH time set-up time START condition data hold time data set-up time set-up time STOP condition SCL and SDA rise time SCL and SDA fall time bus free time between STOP and START capacitive load for each bus line pulse width of allowable spikes noise margin at LOW level noise margin at HIGH level 100 - - - - 0.9 - - 300 300 - 400 50 - - kHz s s s s s ns s ns ns s pF ns V V Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver SYMBOL PARAMETER CONDITIONS MIN. - - 100 60 - 17 650 - TYP. TZA3012AHW MAX. UNIT RF input; pins IN1, INQ1, IN2 and IN2Q Vi(p-p) Vsl Zi iso Vi(p-p) SRSSI input voltage swing (peak-to-peak value) typical slice level range input impedance between channel isolation single-ended; note 7 note 5 differential 12 -50 80 - single-ended see Fig.3 Vi = 30 mV (p-p); PRBS (231-1) input 30 to 3200 Mbits/s; PRBS (231-1); VCC = 3.14 to 3.47 V; T = 120 C 5 15 560 -50 500 +50 120 - 500 19 740 +50 dB mV Received Signal Strength Indicator (RSSI) input voltage swing (peak-to-peak value) RSSI sensitivity mV mV/dB mV mV VRSSI(30mV) output voltage VRSSI output voltage variation Output; pins RSSI1 and RSSI2 Zo IO(source) IO(sink) hys ta td Vi(p-p) VI Zi fCREF fCREF output impedance output source current output sink current - - - note 6 Vi(p-p) = 3 dB Vi(p-p) = 3 dB single-ended - - - 50 VCC - 1 single-ended to VCC for SDH/SONET operation see Table 8; R = 1, 2, 4 or 8 40 -20 18 x R 1 - - 2.5 - - - - 50 - 10 1 0.4 - 5 5 mA mA LOS detector hysteresis assert time de-assert time dB s s mV V ppm MHz Reference frequency input; pins CREF and CREFQ input voltage (peak-to-peak value) input voltage input impedance reference clock frequency accuracy requirement reference clock frequency 1000 VCC + 0.25 60 +20 19.44 x R 21 x R PLL characteristics tacq tacq(pc) tacq(o) TDR acquisition time 30 Mbits/s - - - - - - - 1000 200 10 10 - s ms s bits acquisition time at power cycle 30 Mbits/s acquisition time octave change 30 Mbits/s transitionless data run 30 Mbits/s 2002 Sep 10 38 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver SYMBOL Jitter tolerance Jtol(p-p) jitter tolerance (peak-to-peak value) STM1/OC3 mode (ITU-T G.958); PRBS (231-1) f = 6.5 kHz f = 65 kHz f = 1 MHz STM4/OC12 mode (ITU-T G.958); PRBS (231-1) f = 25 kHz f = 250 kHz f = 5 MHz STM16/OC48 mode (ITU-T G.958); PRBS (231-1) f = 100 kHz f = 1 MHz f = 20 MHz Notes 3 0.3 0.3 10 1 0.5 3 0.3 0.3 >10 >1 >0.5 3 0.3 0.3 >10 >1 >0.5 PARAMETER CONDITIONS MIN. TYP. TZA3012AHW MAX. UNIT - - - UI UI UI - - - UI UI UI - - - UI UI UI 1. Default settings: UI = LOW (pre-programmed mode, see Table 1); DR0 = LOW, DR1 = HIGH, DR2 = LOW (STM16/OC48); INSEL = HIGH (limiter 1 is active); WINSIZE = HIGH (1000 ppm); ENBA = HIGH (automatic byte alignment); ENLOUTQ = HIGH (DOUT, COUT disabled); ENLINQ = HIGH (DLOOP, CLOOP disabled); DMXR0 = HIGH, DMXR1 = HIGH (DMX ratio is 1 : 16); CREF(Q) = 19.44 MHz; LOSTH2 is not connected (LOS2 switched off); D00(Q) to D15(Q), FP(Q), PARITY(Q), POCLK(Q) and PRSCLO(Q) are not connected. 2. The output swing is adjustable in 16 steps controlled by bits RFS in I2C-bus register CBH. 3. The output swing is adjustable in 16 steps controlled by bits MFS in I2C-bus register C8H. In standard LVPECL mode only swing = 12 (default) should be used. 4. With 50% duty cycle. 5. The slice level is adjustable in 256 steps controlled by I2C-bus registers C0H and C1H. 6. The hysteresis is adjustable in 8 steps controlled by bits HYS1 and HYS2 in I2C-bus registers BDH and BFH. 7. The RF input is protected against a differential overvoltage; the maximum input current is 30 mA. 2002 Sep 10 39 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver TZA3012AHW handbook, full pagewidth MBL556 50 ICCD (mA) 40 LVPECL standard 30 CML AC/DC 20 LVPECL floating 10 0 0 5 10 15 value of address C8H, bit 3 to bit 0 Fig.12 Suply current per parallel output. handbook, full pagewidth MBL557 1000 Vo(p-p) (mV) 800 LVPECL standard 600 LVPECL floating DEFAULT CML AC/DC 400 200 0 0 5 10 15 value of address C8H, bit 3 to bit 0 Fig.13 Output voltage swing of parallel output. 2002 Sep 10 40 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver TZA3012AHW handbook, full pagewidth MBL558 50 ICCD (mA) 40 CML AC 30 20 10 0 0 5 10 15 value of address CBH, bit 3 to bit 0 Serial outputs are default off. Fig.14 Supply current per serial output. handbook, full pagewidth MBL559 1000 Vo(p-p) (mV) 800 600 CML AC (clock 2.4 GHz) 400 (ENLOUTQ = LOW) 200 0 0 5 10 15 value of address CBH, bit 3 to bit 0 Fig.15 Output voltage swing of serial output. 2002 Sep 10 41 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver TZA3012AHW handbook, full pagewidth SWING CONTROL VCC Vterm transmission lines 50 2V optional AC coupling OUT Iswing OUTQ 50 to highimpedance input 50 in 50 on-chip off-chip MBL562 Fig.16 Standard PECL mode. handbook, full pagewidth SWING CONTROL VCC OUT transmission lines 50 to high impedance input Iswing OUTQ 50 100 in on-chip off-chip MBL560 Fig.17 Floating PECL mode (DC coupled). 2002 Sep 10 42 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver TZA3012AHW handbook, full pagewidth SWING CONTROL VCC Vbias AC coupling OUT transmission lines 50 Iswing OUTQ 50 50 50 to high impedance input in on-chip off-chip MBL561 Fig.18 Floating LVPECL mode (AC coupled). handbook, full pagewidth recommended for serial outputs VCC 120 100 100 SWING CONTROL 100 100 50 transmission lines 50 50 OUT Iswing OUTQ 50 to highimpedance input in on-chip off-chip MBL563 Fig.19 CML AC coupled mode. 2002 Sep 10 43 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver TZA3012AHW handbook, full pagewidth SWING CONTROL VCC Vbias 50 transmission lines 50 to high impedance input 50 100 100 OUT Iswing OUTQ 50 in on-chip off-chip MBL564 Fig.20 CML DC coupled mode. handbook, full pagewidth COUT t D-C DOUT MGU345 The timing is measured from the cross-over point of the clock output signal to the cross-over point of the data output (all signals are differential). Fig.21 Loop mode output timing. 2002 Sep 10 44 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver TZA3012AHW handbook, halfpage CLOOP td tsu th DLOOP MBL554 The timing is measured from the cross-over point of the clock input signal to the cross-over point of the data input. Fig.22 Loop mode input timing. handbook, full pagewidth POCLK t D-C D00 to D15, FP, PARITY MGU343 The timing is measured from the cross-over point of the clock output signal to the cross-over point of the data output (all signals are differential). Fig.23 Parallel bus output timing. 2002 Sep 10 45 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver PACKAGE OUTLINE HTQFP100: plastic, heatsink thin quad flat package; 100 leads; body 14 x 14 x 1.0 mm TZA3012AHW SOT638-1 c y heatsink side X Dh 75 76 51 50 ZE A e E HE wM bp pin 1 index Lp L detail X Eh A A2 A1 (A3) 100 1 wM ZD 25 bp D HD 26 e vM A B vM B 0 scale DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.2 A1 0.15 0.05 A2 1.05 0.95 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D(1) 14.1 13.9 Dh 7.1 6.1 E(1) 14.1 13.9 Eh 7.1 6.1 e 0.5 HD 10 mm HE L 1.0 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 ZD(1) ZE(1) 1.15 0.85 1.15 0.85 7 0 16.15 16.15 15.85 15.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT638-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 01-03-30 2002 Sep 10 46 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. TZA3012AHW If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 2002 Sep 10 47 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not suitable(3) TZA3012AHW SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable suitable not not recommended(4)(5) recommended(6) 1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2002 Sep 10 48 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS TZA3012AHW This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Preliminary data Qualification Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2002 Sep 10 49 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver PURCHASE OF PHILIPS I2C COMPONENTS TZA3012AHW Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2002 Sep 10 50 Philips Semiconductors Preliminary specification 30 Mbits/s up to 3.2 Gbits/s A-rateTM fibre optic receiver NOTES TZA3012AHW 2002 Sep 10 51 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. (c) Koninklijke Philips Electronics N.V. 2002 SCA74 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 403510/01/pp52 Date of release: 2002 Sep 10 Document order number: 9397 750 08086 |
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